From dakott@alpha.delta.edu Thu Jan 1 05:56:53 1998 Received: from aleve.media.mit.edu by hub.media.mit.edu; (5.65v3.2/1.1/06Jun95-8.2MPM) id AA29720; Thu, 1 Jan 1998 05:56:53 -0500 Received: from kott.my.domain (root@pm233-26.dialip.mich.net [198.110.144.127]) by aleve.media.mit.edu (8.8.7/ML970927) with ESMTP id FAA31795 for ; Thu, 1 Jan 1998 05:06:14 -0500 (EST) Received: from kott.my.domain (dakott@kott.my.domain [192.168.0.1]) by kott.my.domain (8.8.8/8.8.5) with SMTP id FAA01072 for ; Thu, 1 Jan 1998 05:06:33 -0500 (EST) Date: Thu, 1 Jan 1998 05:06:32 -0500 (EST) From: David Kott Sender: dakott@kott.my.domain To: handyboard@media.mit.edu Subject: Re: Digital outputs. In-Reply-To: <199712312227.QAA03595@augusta.netperceptions.com> Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Wed, 31 Dec 1997, Tom Brusehaver wrote: > > G> Wich are the options to have 3 digital outputs in the handyboard? > G> No matter if i have to do little modifications to the Hardware. I > G> already know how to conect the keypad if you can tell me how > G> obtain 3 outputs.. :) > > > The SPI port is sitting there. I think you can get at 3 outputs from > those pins (SD/RD/CLK). > yet ANOTHER idea, if you are suitably masochistic, is to use the SPI port for a much more extensible I/O system. As you know, SPI uses 4 basic control signals, MOSI, MISO, CLK and SS... Ok, what we used to do in Embedded Controllers class is hook up a Serial In/Parallel Out (hereforward referred to as a SIPO) shift register. You must have at least ONE output available, so, this pretty much eliminates a L293 or, if you are bold enough, obtain additional outputs using a '138 as outlined in the HandyBoard FAQ. A SIPO you might use is the 8 bit 74164. Hook the DATA IN on the SIPO to the MOSI pin on the SPI. Hook the SPI's CLK output to the SIPO's clock pin. Use a transparent latch to update and hold the data on the outputs of the SIPO and update it with the one output pin, perhaps a 74373. To update the new 8 bits of data appearing at your latch's output, you load the SPI's data register with the byte value that you want to have across your new outputs. This data will be shifted out during the next 8 E-clock cycles. After the SPI's data register is empty indicating that the SIPO has the output byte on it's parallel outputs, pulse the single control output to update the latch's outputs. With this arrangement, you could, in theory, have many, many SIPO shift register/Latch pairs; the Serial Data In of the next stage connected to the last Parallel Output on the previous adjacent stage. One would just have to make sure that you coordinated the number of stages with the number of bytes outshifted by the SPI data register (naturally). The downside to this arrangement is the time it takes to update a digital output. The entire train (8 bits, 16 bits, 24 bits... more?) Need to be loaded and shifted out to change just ONE output. The upside is, the data will shift at 2 Mhz, which makes for a (250 ns * [8+2] ) 2.5 ms update time. Not suitable for time critical applications, (PWM, Communication) but not bad for bulk outputs. I don't think I have explained my little circuit here very well.. perhaps an ASCII graphic? Output originally going to an L293D +---------------------------------------+ |Or added via a '138 from the | |expansion buss. | | +--+----+ +----+---------+ +---------+ | LE | | | SPI CLK |'164 PO0|----| '373 |---- | +-----------+ CP PO1|----| |---- | 68HC11 | SPI MOSI | PO2|----| |---- | +-----------+ Data PO3|----| |---- New | | | PO4|----| |---- Digital +--------------+ | PO5|----| |---- Outputs | PO6|----| |---- | PO7|----| |---- +---------+ +-------+ Where: PO# is a "Parallel Output" on a SIPO Data is the "Serial Data Input" on a SIPO CP is the SIPO's clock -d Win95/NT - 32 bit extensions and a graphical shell for a 16 bit patch to an 8 bit operating system originally coded for a 4 bit microprocessor, written by a 2 bit company that can't stand 1 bit of competition. -UGU