// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009-2012 by Wilson Snyder.

`ifndef _V_SV_PKG_
 `define _V_SV_PKG_

package v_sv_pkg;
   typedef logic [7:0]  byte_t;
endpackage

`endif // guard